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18-mbit (512k x 36/1m x 18) flow-through sram cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05547 rev. *e revised feburary 14, 2007 features ? supports 133 mhz bus operations ? 512k x 36/1m x 18 common io ? 2.5v core power supply (v dd ) ? 2.5v io supply (v ddq ) ? fast clock-to-output times, 6.5 ns (133 mhz version) ? provides high-performance 2-1-1-1 access rate ? user selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self timed write ? asynchronous output enable ? cy7c1381dv25/cy7c1383dv25 available in jedec-standard pb-free 100-pin tqfp, pb-free and non pb-free 165-ball fbga package. cy7c1381fv25/cy7c1383fv25 available in pb-free and non pb-free 119-ball bga package ? ieee 1149.1 jtag-compatible boundary scan ? zz sleep mode option functional description [1] the cy7c1381dv25/cy7c1383dv25/cy7c1381fv25/ cy7c1383fv25 is a 2.5v, 512k x 36 and 1m x 18 synchronous flow through srams, designed to interface with high-speed microprocessors with minimum glue logic. maximum access delay from clo ck rise is 6.5 ns (133 mhz version). a 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. all syn chronous inputs are gated by registers controlled by a positive edge triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address pipelining chip enable (ce 1 ), depth expansion chip enables (ce 2 and ce 3 [2] ), burst control inputs (adsc , adsp , and adv ), write enables ( bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. the cy7c1381dv25/cy7c1383dv25/cy7c1381fv25/ cy7c1383fv25 allows interleaved or linear burst sequences, selected by the mode input pin. a high selects an interleaved burst sequence, while a low selects a linear burst sequence. burst accesses can be initiated with the processor address strobe (adsp ) or the cache controller address strobe (adsc ) inputs. address advancement is controlled by the address advancement (adv ) input. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). the cy7c1381dv25/cy7c1383dv25/cy7c1381fv25/ cy7c1383fv25 operates from a +2.5v core power supply while all outputs also operate with a +2.5 supply. all inputs and outputs are jedec-standard and jesd8-5-compatible. selection guide 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 210 175 ma maximum cmos standby current 70 70 ma notes 1. for best practices or recommendations, please refer to the cypress application note an1064, sram system design guidelines on www.cypress.com . 2. ce 3, ce 2 are for tqfp and 165 fbga package only. 119 bga is offered only in 1 chip enable. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 2 of 28 logic block diagram ? cy7c1381dv25/cy7c1381fv25 [3] (512k x 36) logic block diagram ? cy7c1383dv25/cy7c1383fv25 [3] (1m x 18) address register burst counter and logic clr q1 q0 enable register sense amps output buffers input registers memory array mode a [1:0] dqs dqp a dqp b dqp c dqp d a0, a1, a adv clk adsp adsc bw d bw c bw b bw a bwe ce1 ce2 ce3 oe gw sleep dq a , dqp a byte write register dq b , dqp b write register dq c , dqp c write register byte write register dq d , dqp d byte write register dq d , dqp d byte write register dq c , dqp c write register dq b , dqp b write register dq a , dqp byte write register address register adv burst counter and q1 q0 ce 1 oe sense amps memory array output buffers input registers mode ce 2 ce 3 gw bwe a0,a1,a bw b bw a dq b ,dqp b dq a ,dqp a enable a[1:0] dqs dqp a dqp b dq b ,dqp b write driver dq a ,dqp a write driver sleep control note 3. cy7c1381fv25 and cy7c1383fv25 have only 1 chip enable (ce 1 ). [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 3 of 28 pin configurations a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1381dv25 (512k x 36) nc a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1383dv25 (1 mbit x 18) nc 100-pin tqfp pinout (3 chip enable) a a [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 4 of 28 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u v ddq nc/288m nc/144m dqp c dq c dq d dq c dq d aa aa adsp v ddq aa dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/576m nc/1g nc nc tdo tck tdi tms nc/36m nc/72m nc v ddq v ddq v ddq aaa a a a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc bwe bw d zz 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc/288m nc/144m nc dq b dq b dq b dq b aa aa adsp v ddq aa nc v ddq nc v ddq v ddq v ddq nc nc nc nc/72m v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/576m nc/1g nc nc tdo tck tdi tms a a nc v ddq v ddq v ddq a nc/36m a a a a a a a a a a0 a1 dq a dq b nc nc dq a nc dq a dq a nc nc dq a nc dq a nc dq a nc dq a v dd nc dq b nc v dd dq b nc dq b nc adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss nc mode dqp b dqp a nc bw b nc v dd nc bw a nc bwe nc zz cy7c1383fv25 (1m x 18) cy7c1381fv25 (512k x 36) 119-ball bga pinout [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 5 of 28 pin configurations (continued) 165-ball fbga pinout (3 chip enable) cy7c1381dv25 (512k x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce 2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc/36m nc/72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a cy7c1383dv25 (1mx 18) a0 a v ss 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m nc nc dqp b v ss dq b ace 1 nc ce 3 bw b bwe a ce 2 nc dq b dq b mode nc dq b dq b nc nc nc nc/36m nc/72m v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc/576m v ss v ddq nc/1g dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a a [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 6 of 28 pin definitions name io description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 [2] are sampled active. a [1:0] feed the 2-bit counter. bw a , bw b bw c , bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw [a:d] and bwe ). clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 [2] to select or deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 [2] to select or dese lect the device. ce 2 is sampled only when a new external address is loaded. ce 3 [2] input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or deselect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the io pins. when low, the io pins behave as outputs. wh en deasserted high, io pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal. sampled on the rising edge of clk. when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the dev ice are captured in t he address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the dev ice are captured in t he address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized . bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. zz input- asynchronous zz sleep input . this active high input places the device in a non-time critical sleep condition with data integrity preserved. for no rmal operation, this pin has to be low or left floating. zz pin has an internal pull down. dq s io- synchronous bidirectional data io lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as out puts, they deliver the data contained in the memory location specified by the addresses pres ented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq s and dqp x are placed in a tri-stat e condition.the outputs are automatically tri-stated during the data port ion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp x io- synchronous bidirectional data parity io lines. functionally, these signals are identical to dq s . during write sequences, dqp x is controlled by bw x correspondingly. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 7 of 28 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t cdv ) is 6.5 ns (133 mhz device). the cy7c1381dv25/cy7c 1383dv25/cy7c1381fv25/ cy7c1383fv25 supports secondary cache in systems using a linear or interleaved burst sequence. the interleaved burst order supports pentium ? and i486? processors. the linear burst sequence is suited for proc essors that use a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the proc essor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burs t counter captur es the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualifie d with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 [2] ) and an asynchronous output enable (oe ) provide for easy bank selection and output tr i-state control. adsp is ignored if ce 1 is high. single read accesses a single read access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 [2] are all asserted active, and (2) adsp or adsc is asserted low (if the access is initiated by adsc , the write inputs must be deserted during this first cycle). the address presented to the address inputs is latched into the address register and the burst counter and/or control logic, and presented to the memory core. if the oe input is asserted low, the requested data will be available at the data outputs with a maximum to t cdv after clock rise. adsp is ignored if ce 1 is high. single write accesses initiated by adsp this access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , ce 3 [2] are all asserted active, and (2) adsp is asserted low. the addresses presented are loaded into the address register and the burst inputs (gw , bwe , and bwx ) are ignored during this first clock cycle. if the write inputs ar e asserted active (see truth table for read/write [4, 9] on page 10 for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. byte writes are allowed. all ios are tri-stated during a byte write. as this is a common io device, the asynchronous oe input signal must be deserted mode input-static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and must remain static during device operation. mode pin has an internal pull up. v dd power supply power supply inputs to the core of the device . v ddq io power supply power supply for the io circuitry . v ss ground ground for the core of the device . v ssq io ground ground for the io circuitry . tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negativ e edge of tck. if the jtag feature is not used, this pin can be left unconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be left floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to th e jtag circuitry . if the jtag feature is not used, this pin must be connected to v ss . this pin is not available on tqfp packages. nc, nc/(36m, 72m, 144m, 288m, 576m, 1g) - no connects . not internally connected to the di e. 36m, 72m, 144m, 288m, 576m, and 1g are address expansion pins and are not internally connected to the die. v ss /dnu ground/dnu this pin can be connected to ground or can be left floating. pin definitions (continued) name io description [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 8 of 28 and the ios must be tri-stated pr ior to the presentation of data to dqs. as a safety precauti on, the data lines are tri-stated once a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc this write access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 [2] are all asserted active, (2) adsc is asserted low, (3) adsp is deserted high, and (4) the write input signals (gw , bwe , and bw x ) indicate a write access. adsc is ignored if adsp is active low. the addresses presented are loaded into the address register and the burst counter, the contro l logic, or both, and delivered to the memory core. the information presented to dq x will be written into the specified addre ss location. byte writes are allowed. all ios are tri-stated when a write is detected, even a byte write. since this is a common io device, the asynchronous oe input signal must be deasserted and the ios must be tri-stated prior to the presentation of data to dqs. as a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1381dv25/cy7c 1383dv25/cy7c1381fv25/ cy7c1383fv25 provides an on-chip two-bit wraparound burst counter inside the sram. the burst counter is fed by a [1:0] , and can follow either a linear or interleaved burst order. the burst order is determined by t he state of the mode input. a low on mode will select a linear burst sequence. a high on mode will select an interleaved burst order. leaving mode unconnected will cause the device to default to a interleaved burst sequence. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation sleep mode. two clock cycles are required to enter into or exit from this sleep mode. while in this mode, data integrity is guaranteed. accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the sleep mode. ce 1 , ce 2 , ce 3 [2] , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 80 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current th is parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 9 of 28 truth table [4, 5, 6, 7, 8] cycle description address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselected cycle, power down none h x x l x l x x x l-h tri-state deselected cycle, power down none l l x l l x x x x l-h tri-state deselected cycle, power down none l x h l l x x x x l-h tri-state deselected cycle, power down none l l x l h l x x x l-h tri-state deselected cycle, power down none x x x l h l x x x l-h tri-state sleep mode, power down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes 4. x = don't care, h = logic high, l = logic low. 5. write = l when any one or more byte write enable signals, and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 6. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 7. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of t he write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 8. oe is asynchronous and is not sampled with the clock rise. it is masked internally during writ e cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low). [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 10 of 28 truth table for read/write [4, 9] function (cy7c1381dv25/cy7c1381fv25) gw bwe bw d bw c bw b bw a read h h x x x x read h l h h h h write byte a (dq a , dqp a )hlhhhl write byte b (dq b , dqp b )hlhhlh write bytes a, b (dq a , dq b , dqp a , dqp b )h l h h l l write byte c (dq c , dqp c ) hlhlhh write bytes c, a (dq c , dq a, dqp c , dqp a )hlhlhl write bytes c, b (dq c , dq b, dqp c , dqp b )h l h l l h write bytes c, b, a (dq c , dq b , dq a, dqp c , dqp b , dqp a ) hlhll l write byte d (dq d , dqp d )hllhhh write bytes d, a (dq d , dq a, dqp d , dqp a )h l l h h l write bytes d, b (dq d , dq a, dqp d , dqp a )h l l h l h write bytes d, b, a (dq d , dq b , dq a, dqp d , dqp b , dqp a ) hllhl l write bytes d, b (dq d , dq b, dqp d , dqp b )h l l l h h write bytes d, b, a (dq d , dq c , dq a, dqp d , dqp c , dqp a ) hlllhl write bytes d, c, a (dq d , dq b , dq a, dqp d , dqp b , dqp a ) hllllh write all bytes h l l l l l write all bytes l x x x x x truth table for read/write [4, 9] function (cy7c1383dv25/cy7c1383fv25) gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write all bytes h l l l write all bytes l x x x note 9. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done ba sed on which byte write is active. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 11 of 28 ieee 1149.1 serial boundary scan (jtag) the cy7c1381dv25/cy7c1383dv25 incorporates a serial boundary scan test access port (tap). this part is fully compliant with 1149.1. t he tap operates using jedec-standard 3.3v or 2.5v io logic levels. the cy7c1381dv25/cy7c1383dv25 contains a tap controller, instruction register , boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate t he sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo may be left unconnected. upon power up, the device will come up in a reset state, which will not interfere with the operation of the device. tap controller state diagram the 0 or 1 next to each state represents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see tap controller state diagram . tdi is internally pulled up and can be unconnected if the tap is unu sed in an application. tdi is connected to the most signific ant bit (msb) of any register. (see tap controller block diagram ). test data-out (tdo) the tdo output ball is used to serially clock data out from the registers. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is con nected to the least significant bit (lsb) of any register. (see tap controller state diagram .) tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset in ternally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned in and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is se rially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram . upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identi?cation register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck tms tap controller tdi tdo [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 12 of 28 when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram io ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload, and sample z instructions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. (id) register the id register is loaded with a vendor specific 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions on page 14 . tap instruction set overview eight different instructions ar e possible with the three bit instruction register. all combinations are listed in identification codes on page 15 . three of these instructions are listed as reserved and must not be used . the other five instructions are described in detail below. instructions are loaded into the tap controller during the shift-ir state, when the instru ction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction onc e it is shifted in, the tap controller needs to be mov ed into the update-ir state. extest the extest instruction enables the preloaded data to be driven out through t he system output pins. th is instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. idcode the idcode instruction causes a vendor specific 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction caus es the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. the sample z command places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the captur e-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of t he boundary scan register cells prior to the selection of anot her boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when re quired; that is, while data captured is shifted out, the preloaded data is shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructi on is that it shortens the boundary scan path when multiple devices are connected together on a board. extest output bus tri-state ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #85 (for 119-bga package) or bit #89 (for 165-fbga package). when this scan cell, called the ?e xtest output bus tri-state,? is latched into the preload register during the update-dr state in [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 13 of 28 the tap controller, it will direct ly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell will latch into the preload register. when the extest instruction is entered, this bit will directly control the output q-bus pins. note that this bit is preset high to enable the out put when the device is powered up, and also when the tap controller is in the test-logic-reset state. reserved these instructions are not impl emented but are reserved for future use. do not use these instructions. tap timing tap ac switching characteristics over the operating range [10, 11] parameter descrip tion min. max. unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 20 ns t tl tck clock low time 20 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns setup times t tmss tms setup to tck clock rise 5 ns t tdis tdi setup to tck clock rise 5 ns t cs capture setup to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns t tl test clock (tck) 123456 test mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined notes 10. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 11. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 14 of 28 2.5v tap ac test conditions input pulse levels .................................................v ss to 2.5v input rise and fall time.............. ............ ........... ................ 1 ns input timing reference levels .........................................1.25v output reference levels............ .....................................1.25v test load termination supply voltage.............................1.25v 2.5v tap ac output load equivalent tdo 1.25v 20pf z = 50 ? o 50 ? (0c < ta < +70c; v dd = 2.5v 0.125v unless otherwise noted) [12] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ?1.0 ma, v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a, v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma, v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a identification register definitions instruction field cy7c1381dv25/ cy7c1381fv25 (512k x 36) cy7c1383dv25/ cy7c1383fv25 (1 mbit x 18) description revision number (31:29) 000 000 describes the version number device depth (28:24) 01011 01011 reserved for internal use. device width (23:18) 119-bga 101001 101001 defines the memory type and architecture device width (23:18) 165-fbga 000001 000001 defines the memory type and architecture cypress device id (17:12) 100101 0 10101 defines the width and density cypress jedec id code (11:1) 00000110100 0000011010 0 allows unique identification of sram vendor id register presence indicator (0) 1 1 indicates the presence of an id register scan register sizes register name bit size (x36) bit size (x18) instruction bypass 3 3 bypass 1 1 id 32 32 boundary scan order (119-ball bga package) 85 85 boundary scan order (165-ball fbga package) 89 89 note 12. all voltages referenced to v ss (gnd). [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 15 of 28 identification codes instruction code description extest 000 captures io ring contents. places th e boundary scan register between tdi and tdo. forces all sram outputs to high-z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures io ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use. this instru ction is reserved for future use. sample/preload 100 captures io ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use. this instru ction is reserved for future use. reserved 110 do not use. this instru ction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. 119-ball bga boundary scan order [13, 14] bit # ball id bit # ball id bit # ball id bit # ball id 1 h4 23 f6 45 g4 67 l1 2t424e746a468m2 3t5 25 d7 47 g3 69 n1 4t626h748c370p1 5r5 27 g6 49 b2 71 k1 6l528e650b372l2 7r6 29 d6 51 a3 73 n2 8u630c752c274p2 9r731b753a275r3 10 t7 32 c6 54 b1 76 t1 11 p6 33 a6 55 c1 77 r1 12 n7 34 c5 56 d2 78 t2 13 m6 35 b5 57 e1 79 l3 14 l7 36 g5 58 f2 80 r2 15 k6 37 b6 59 g1 81 t3 16 p7 38 d4 60 h2 82 l4 17 n6 39 b4 61 d1 83 n4 18 l6 40 f4 62 e2 84 p4 19 k7 41 m4 63 g2 85 internal 20 j5 42 a5 64 h1 21 h6 43 k4 65 j3 22 g7 44 e4 66 2k notes 13. balls that are nc (no connect) are preset low. 14. bit #85 is preset high. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 16 of 28 165-ball bga boundary scan order [13, 15] bit # ball id bit # ball id bit # ball id 1 n6 31 d10 61 g1 2n7 32c11 62 d2 3 n10 33 a11 63 e2 4p11 34b11 64 f2 5 p8 35 a10 65 g2 6 r8 36 b10 66 h1 7r9 37a9 67 h3 8p9 38b9 68 j1 9p10 39c10 69 k1 10 r10 40 a8 70 l1 11 r11 41 b8 71 m1 12 h11 42 a7 72 j2 13 n11 43 b7 73 k2 14 m11 44 b6 74 l2 15 l11 45 a6 75 m2 16 k11 46 b5 76 n1 17 j11 47 a5 77 n2 18 m10 48 a4 78 p1 19 l10 49 b4 79 r1 20 k10 50 b3 80 r2 21 j10 51 a3 81 p3 22 h9 52 a2 82 r3 23 h10 53 b2 83 p2 24 g11 54 c2 84 r4 25 f11 55 b1 85 p4 26 e11 56 a1 86 n5 27 d11 57 c1 87 p6 28 g10 58 d1 88 r6 29 f10 59 e1 89 internal 30 e10 60 f1 note 15. bit #89 is preset high. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 17 of 28 maximum ratings exceeding the maximum ratings may impair the useful life of the device. for user guidelines, not tested. storage temperature ................................. ?65c to +150c ambient temperature with power applied.......................... ................... ?55c to +125c supply voltage on v dd relative to gnd .. ..... ?0.3v to +3.6v supply voltage on v ddq relative to gnd ...... ?0.3v to +v dd dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage ............... .............. ...... ?0.5v to v dd + 0.5v current into outputs (low) ........................................ 20 ma static discharge voltage.......................................... > 2001v (per mil-std-883, method 3015) latch-up current ................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 2.5v 5% 2.5v ? 5% to v dd industrial ?40c to +85c electrical characteristics over the operating range [16, 17] parameter description test conditions min. max. unit v dd power supply voltage 2.375 2.625 v v ddq io supply voltage for 2.5v io 2.375 v dd v v oh output high voltage for 2.5v io, i oh = ?1.0 ma 2.0 v v ol output low voltage for 2.5v io, i ol = 1.0 ma 0.4 v v ih input high voltage [16] for 2.5v io 1.7 v dd + 0.3v v v il input low voltage [16] for 2.5v io ?0.3 0.7 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v dd, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 7.5-ns cycle, 133 mhz 210 ma 10-ns cycle, 100 mhz 175 ma i sb1 automatic ce power down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = f max, inputs switching 7.5-ns cycle, 133 mhz 140 ma 10-ns cycle, 100 mhz 120 i sb2 automatic ce power down current?cmos inputs max. v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 70 ma i sb3 automatic ce power down current?cmos inputs max. v dd , device deselected, v in v ddq ? 0.3v or v in 0.3v, f = f max , inputs switching 7.5-ns cycle, 133 mhz 130 ma 10-ns cycle, 100 mhz 110 ma i sb4 automatic ce power down current?ttl inputs max. v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 80 ma notes 16. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 17. t power up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 18 of 28 capacitance [18] parameter description test conditions 100 tqfp package 119 bga package 165 fbga package unit c in input capacitance t a = 25c, f = 1 mhz, v dd /v ddq = 2.5v 589pf c clk clock input capacitance 5 8 9 pf c io input/output capacitance 5 8 9 pf thermal resistance [18] parameter description test conditions 100 tqfp package 119 bga package 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 28.66 23.8 20.7 c/w jc thermal resistance (junction to case) 4.08 6.2 4.0 c/w ac test loads and waveforms output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 2.5v io test load note 18. tested initially and after any design or proc ess change that may affect these parameters. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 19 of 28 switching characteristics over the operating range [19, 20] parameter description 133 mhz 100 mhz unit min. max. min. max. t power v dd (typical) to the first access [21] 11ms clock t cyc clock cycle time 7.5 10 ns t ch clock high 2.1 2.5 ns t cl clock low 2.1 2.5 ns output times t cdv data output valid after clk rise 6.5 8.5 ns t doh data output hold after clk rise 2.0 2.0 ns t clz clock to low-z [22, 23, 24] 2.0 2.0 ns t chz clock to high-z [22, 23, 24] 0 4.0 0 5.0 ns t oev oe low to output valid 3.2 3.8 ns t oelz oe low to output low-z [22, 23, 24] 00ns t oehz oe high to output high-z [22, 23, 24] 4.0 5.0 ns setup times t as address setup before clk rise 1.5 1.5 ns t ads adsp , adsc setup before clk rise 1.5 1.5 ns t advs adv setup before clk rise 1.5 1.5 ns t wes gw , bwe , bw [a:d] setup before clk rise 1.5 1.5 ns t ds data input setup before clk rise 1.5 1.5 ns t ces chip enable setup 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t adh adsp , adsc hold after clk rise 0.5 0.5 ns t weh gw , bwe , bw [a:d] hold after clk rise 0.5 0.5 ns t advh adv hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 ns notes 19. timing reference level is 1.25v. 20. test conditions shown in (a) of ac test loads unless otherwise noted. 21. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially, before a read or write operation can be initiated. 22. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 23. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not impl y a bus contention condition, bu t reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 24. this parameter is sampled and not 100% tested. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 20 of 28 timing diagrams read cycle timing [25] t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces data out (q) high-z t clz t doh t cdv t oehz t cdv single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 2) q(a2 + 3) a2 adv suspends burst deselect cycle dont care undefined adsp adsc gw, bwe,bw x ce adv oe note 25. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 21 of 28 write cycle timing [25, 26] timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces high-z burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds t weh t wes byte write signals are ignored for ?rst cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined adsp adsc bwe, bw x gw ce adv oe data in (d) data out (q) note 26. full width write can be initiated by either gw low, or by gw high, bwe low and bw x low. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 22 of 28 read/write cycle timing [25, 27, 28] timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a2 t ceh t ces single write d(a3) a3 a4 burst read back-to-back reads high-z q(a2) q(a4) q(a4+1) q(a4+2) q(a4+3) t weh t wes t oehz t dh t ds t cdv t oelz a1 a5 a6 d(a5) d(a6) q(a1) back-to-back writes dont care undefined adsp adsc bwe, bw x ce adv oe data in (d) data out (q) notes 27. the data bus (q) remains in high-z following a write cycle, unless a new read access is initiated by adsp or adsc . 28. gw is high. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 23 of 28 zz mode timing [29, 30] timing diagrams (continued) t zz i supply clk zz t zzrec all inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 29. device must be deselected when entering zz sleep mode. see cy cle descriptions table for all possible signal conditions to de select the device. 30. dqs are in high-z when exiting zz sleep mode. [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 24 of 28 ordering information not all of the speed, package, and temperature ranges are availabl e. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram part and package type operating range 133 cy7c1381dv25-133axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial CY7C1383DV25-133AXC cy7c1381fv25-133bgc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1383fv25-133bgc cy7c1381fv25-133bgxc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1383fv25-133bgxc cy7c1381dv25-133bzc 51-85180 165-ball fine-pitc h ball grid array (13 x 15 x 1.4 mm) cy7c1383dv25-133bzc cy7c1381dv25-133bzxc 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1383dv25-133bzxc cy7c1381dv25-133axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free lndustrial cy7c1383dv25-133axi cy7c1381fv25-133bgi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1383fv25-133bgi cy7c1381fv25-133bgxi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1383fv25-133bgxi cy7c1381dv25-133bzi 51-85180 165-ball fine-pitc h ball grid array (13 x 15 x 1.4 mm) cy7c1383dv25-133bzi cy7c1381dv25-133bzxi 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1383dv25-133bzxi 100 cy7c1381dv25-100axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free commercial cy7c1383dv25-100axc cy7c1381fv25-100bgc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1383fv25-100bgc cy7c1381fv25-100bgxc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1383fv25-100bgxc cy7c1381dv25-100bzc 51-85180 165-ball fine-pitc h ball grid array (13 x 15 x 1.4 mm) cy7c1383dv25-100bzc cy7c1381dv25-100bzxc 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1383dv25-100bzxc cy7c1381dv25-100axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) pb-free lndustrial cy7c1383dv25-100axi cy7c1381fv25-100bgi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1383fv25-100bgi cy7c1381fv25-100bgxi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) pb-free cy7c1383fv25-100bgxi cy7c1381dv25-100bzi 51-85180 165-ball fine-pitc h ball grid array (13 x 15 x 1.4 mm) cy7c1383dv25-100bzi cy7c1381dv25-100bzxi 51-85180 165-ball fine-pitch ball grid array (13 x 15 x 1.4 mm) pb-free cy7c1383dv25-100bzxi [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 25 of 28 package diagrams figure 1. 100-pin thin plastic quad flat pack (14 x 20 x 1.4 mm) (51-85050) note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 51-85050-*b [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 26 of 28 figure 2. 119-ball bga ( 14 x 22 x 2.4 mm) (51-85115) package diagrams (continued) 51-85115-*b [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 27 of 28 ? cypress semiconductor corporation, 2006-2007. the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under pate nt or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express writt en agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support system s where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufa cturer assumes all risk of such use and in doing so indemni fies cypress against all charges. intel and pentium are registered trademarks, and i486 is a trademark of intel corporation. all product and company names mentioned in this document are the trademarks of their respective holders. figure 3. 165-ball fbga (13 x 15 x 1.4 mm) (51-85180) package diagrams (continued) a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25mcab ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 -0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180-*a 165 fbga 13 x 15 x 1.40 mm bb165d/bw165d a 1 pin 1 corner 15.000.10 13.000.10 7.00 1.00 ?0.50 (165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.350.06 seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a a 15.000.10 13.000.10 b c 1.00 5.00 0.36 - 0.06 +0.14 1.40 max. solder pad type : non-solder mask defined (nsmd) notes : package weight : 0.475g jedec reference : mo-216 / design 4.6c package code : bb0ac 51-85180-*a [+] feedback [+] feedback
cy7c1381dv25, cy7c1381fv25 cy7c1383dv25, cy7c1383fv25 document #: 38-05547 rev. *e page 28 of 28 document history page document title: cy7c1381dv25/cy7c1383dv25/cy7c13 81fv25/cy7c1383fv25, 18-mb it (512k x 36/1m x 18) flow-through sram document number: 38-05547 rev. ecn no. issue date orig. of change description of change ** 254518 see ecn rkf new data sheet *a 288531 see ecn syt edited description under ?ieee 1149.1 serial boundary scan (jtag)? for non-compliance with 1149.1 removed 117mhz speed bin added pb-free information for 100-pin tqfp, 119 bga and 165 fbga packages added comment of ?pb-free bg pack ages availability? below the ordering information *b 326078 see ecn pci address expansion pins/balls in the pinouts for all packages are modified as per jedec standard added description on extest output bus tri-state changed description on the tap instruction set overview and extest changed device width (23:18) for 119-bga from 000001 to 101001 added separate row for 165 -fbga device width (23:18) changed ja and jc for tqfp package from 31 and 6 c/w to 28.66 and 4.08 c/w respectively changed ja and jc or bga package from 45 and 7 c/w to 23.8 and 6.2 c/w respectively changed ja and jc for fbga package from 46 and 3 c/w to 20.7 and 4.0 c/w respectively modified v ol, v oh test conditions removed comment of ?pb-free bg pack ages availability? below the ordering information updated ordering information table *c 416321 see ecn nxr changed address of cypress se miconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed the description of i x from input load current to input leakage current on page# 17 changed the i x current values of mode on page # 18 from ?5 a and 30 a to ?30 a and 5 a changed the i x current values of zz on page # 18 from ?30 a and 5 a to ?5 a and 30 a changed v ih < v dd to v ih < v dd on page # 18 replaced package name column with package diagram in the ordering information table *d 475009 see ecn vkn converted from preliminary to final. added the maximum rating for supply voltage on v ddq relative to gnd changed t th , t tl from 25 ns to 20 ns and t tdov from 5 ns to 10 ns in tap ac switching characteristics table. updated the ordering information table. *e 793579 see ecn vkn added part numbers cy7c1381fv25 and cy7c1383fv25 added footnote# 3 regarding chip enable updated ordering information table [+] feedback [+] feedback

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